
W9864G6JH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
C omma nd
Read
BST
DQ
Q0
Q1
Q2
Q3
Q4
( b )CAS latency = 3
C omma nd
Read
BST
DQ
Q0
Q1
Q2
Q3
Q4
(2) Write cycle
C omma nd
Write
BST
DQ
Q0
Q1
Q2
Q3
Q4
Note:
BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
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7
8
9
10
11
(1) Read cycle
(a) CAS latency =2
Command
Read
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(b) CAS latency =3
Command
Read
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(2) Write cycle
Command
Write
PRCG
tWR
DQM
DQ
Q0
Q1
Q2
Q3
Q4
Publication Release Date: Jun. 25, 2013
- 39 -
Revision A04